1. Field of the Invention
This invention relates to technology for dynamic burn-in testing of synchronous DRAM.
2. Description of the Related Art
Dynamic RAMs (referred to hereinafter as DRAMs) are being widely manufactured and sold as computer products become more widely used. To increase the reliability of DRAMs, it is important to test their lifetimes. When this is done, in order to shorten the testing time, in general an accelerated lifetime test called a burn-in test is performed.
In a burn-in test, power supply voltage and temperature corresponding to more severe conditions than will be encountered in actual use are applied to the DRAM, and the DRAM is operated for a fixed time. Then the operating performance of the DRAM is tested under these operating conditions just as is done in normal operation.
Specifically, during a burn-in test, it is necessary for data to be written in to an arbitrary address in the DRAM.
In conventional DRAM, this operation is determined by a combination of an RAS signal (a row address signal) and a CAS (a column address signal). When in normal mode, the address is specified and write-in or read-out is specified by changing the logical state of the RAS signal, then changing the logical state of the CAS signal.
However, when the mode is specified so that the logical state of the CAS signal is changed before the logical state of the RAS signal, the DRAM automatically goes into refresh mode. As a result, inside the DRAM the address value is automatically counted up from 0 to its maximum value, and refresh operation is executed. A mode such as this is called a CBR (CAS Before RAS) mode.
In burn-in testing of a conventional DRAM, the CBR mode described above is used. That is to say, during the burn-in test, by specifying a waveform pattern that combines an RAS signal with a CAS signal with respect to the conventional DRAM for the purpose of putting it into CBR mode, the conventional DRAM automatically goes into refresh mode. As a result, inside the conventional DRAM, the address value is automatically counted up from 0 to its maximum value, and access to all addresses is executed. In this way, a result equivalent to a test in which writing in was conducted to all addresses is obtained, and the burn-in test is completed.
Thus, it is possible to execute a burn-in test merely by specifying a fixed combined waveform pattern of an RAS signal and a CAS signal in order to put a conventional DRAM into CBR mode. That is to say, it is sufficient for the waveform pattern generating device used for the burn-in test to have a function that can generate a fixed waveform pattern, so it is not required to have complicated functions. Such a burn-in test, which is performed using a fixed waveform pattern, is generally called a static burn-in test.
Recently, synchronous DRAMs (abbreviated below as SDRAMs) have become the most common type of DRAM used, in place of conventional DRAMs.
An SDRAM is characterized by having its input/output and hold operation determined so as to be synchronized with a clock pulse applied to the clock pin. Specifically, whereas, in a conventional DRAM, data input and output are synchronized with timing determined by a combination of an RAS waveform and a CAS waveform as described above, in an SDRAM, the data are input and output continuously with timing synchronized with the clock pulse independently of the RAS signal and the CAS signal. In this way, in an SDRAM the data input/output operation can be executed faster than in a conventional DRAM.
However, in an SDRAM, when an operation is started, a precharge operation is firstly executed for all of the banks; then the following mode setting becomes necessary.
First it is necessary to set a burst length. As was stated above, in a conventional DRAM the operation timing is determined by the RAS signal and the CAS signal, so 100ns (nanoseconds) is necessary for each input or output. By comparison, in an SDRAM, as stated above, data can be input and output continuously on timing synchronized with the clock pulse. The number of data that are input or output in succession is called the burst length. In an SDRAM when the operation starts it is necessary to set this burst length in an internal register.
Next, a CAS latency setting is necessary. In an SDRAM, as stated above, data can be input or output continuously with timing synchronized with a clock pulse, so that there are cases in which the operation of the CPU and external devices cannot keep up with the operation of the SDRAM. In order to adjust for the difference in operation speeds between itself and external devices, the SDRAM can be set so that input and output are executed with a fixed delay with respect to the clock pulse. This delay value is called the CAS latency. In an SDRAM, when the operation starts this CAS latency must be set by means of an internal resistor.
Thus, in an SDRAM when the operation starts, precharging operation is executed for all of the banks; then it is necessary to set the burst length and the CAS latency. In addition, bank switching operation is also necessary.
The various initial settings and the bank switching described above are accomplished by feeding the specified RAS signal and the CAS specified signal corresponding to each state, specified address values, specified data values, etc. to the SDRAM.
Consequently, when a burn-in test is performed on an SDRAM, a static burn-in test such as would be performed on a conventional DRAM is inadequate; it becomes necessary to apply waveform patterns that change dynamically to each of the respective input/output pins and address pins of the SDRAM. This kind of burn-in test that is performed with a dynamically varying waveform pattern is generally called a dynamic burn-in test. In a burn-in test of an SDRAM, it is necessary to dynamically supply at least several tens of waveform patterns.
In order to perform this kind of dynamic burn-in test, in the past it has been necessary to use a waveform generation device that could dynamically generate all of the waveform patterns. In order to generate all of those waveform patterns, it was necessary for the waveform generating device to have the capability to flexibly generate both the well-known NRZ (non-return zero) waveforms and the well-known RZ (return zero) waveforms.
However, a waveform generating device that can dynamically generate both an NRZ waveform and an RZ waveform requires a capability to achieve complicated timing control, raising the problem that in general these devices are very expensive.